intel_pmu plugin¶


Plugin name	`intel_pmu`
Type	read
Callbacks	config, init, read, shutdown
Status	supported
Since	5.8
Copyright	2017–2018 Intel Corporation
Configuration	collectd.conf(5)

The intel_pmu plugin collects information provided by Linux perf interface which provides rich generalized abstractions over hardware specific capabilities. All events are reported on a per core basis.

Performance counters are CPU hardware registers that count hardware events such as instructions executed, cache-misses suffered, or branches mispredicted. They form a basis for profiling applications to trace dynamic control flow and identify hotspots.

For a full description of available options please refer to the collectd.conf(5) manual page.

Synopsis¶

- → See: Plugin-Intel-PMU-Config

 <Plugin intel_pmu>
    ReportHardwareCacheEvents true
    ReportKernelPMUEvents true
    ReportSoftwareEvents true
    EventList "/var/cache/pmu/GenuineIntel-6-2D-core.json"
    HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
    Cores "0" "1,35" "[12-17]"
    DispatchMultiPmu false
  </Plugin>

For a full description of available options please refer to the collectd.conf(5) manual page.

Parameters¶

Name	Description	Comment
Interval	The interval within which to retrieve statistics on monitored events in seconds	Interval option is supported by collectd and is defined in block. No additional functionality should be developed in intel_pmu plugin to support this option.
ReportHardwareCacheEvents	Enable/disable monitoring of hardware cache events
ReportKernelPMUEvents	Enable/disable monitoring of kernel PMU events
ReportSoftwareEvents	Enable/disable monitoring of software vents
EventList	Path to hardware events list file for current CPU.	File can be downloaded by event_download.py script which is part of pmu-tools package.
HardwareEvents	String containing comma separated list of hardware specific events to monitor
Cores	Core groups definition. Monitored metrics are reported only for configured cores. If this option is omitted all available cores are monitored. If a group is enclosed in square brackets each core is added individually to a separate group (that is statistics are not aggregated).	Allowed formats: "0,1,2,3" "0-3" "[0-3]"
DispatchMultiPmu	Enable/disable dispatching of cloned multi PMU for uncore events. If disabled only total sum is dispatched as single event. If enabled separate metric is dispatched for every counter.	Allowed values: true or false Uncore event example: UNC_CHA_DIR_LOOKUP.NO_SNP. If enabled information about event type is added to type_instance, e.g.: "UNC_CHA_DIR_LOOKUP.NO_SNP:type=30". It allows to distinguish between multiple counters for one event.

Metrics¶

Metric/ Feature/Input	Name	Date Type	Format Example	Description	Dependencies	Limitations	Comments
Metric	L1-dcache-loads	Integer	23734	Level 1 cache for data (L1d) read accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-dcache-load-misses	Integer	23734	Level 1 cache for data (L1d) read misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-dcache-stores	Integer	23734	Level 1 cache for data (L1d) writes by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-dcache-store-misses	Integer	23734	Level 1 cache for data (L1d) write misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-dcache-prefetches	Integer	23734	Level 1 cache for data (L1d) prefetch accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-dcache-prefetch-misses	Integer	23734	Level 1 cache for data (L1d) prefetch misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-icache-loads	Integer	23734	Level 1 cache for instructions (L1i) read accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-icache-load-misses	Integer	23734	Level 1 cache for instructions (L1i) read misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-icache-prefetches	Integer	23734	Level 1 cache for instructions (L1i) prefetch accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	L1-icache-prefetch-misses	Integer	23734	Level 1 cache for instructions (L1i) prefetch misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	LLC-loads	Integer	23734	Last level cache (LLC) read accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	LLC-load-misses	Integer	23734	Last level cache (LLC) read misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	LLC-stores	Integer	23734	Last level cache (LLC) writes by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	LLC-store-misses	Integer	23734	Last level cache (LLC) write misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	LLC-prefetches	Integer	23734	Last level cache (LLC) prefetch accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	LLC-prefetch-misses	Integer	23734	Last level cache (LLC) prefetch misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	dTLB-loads	Integer	23734	Translation lookaside buffer for data (dTLB) read accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	dTLB-load-misses	Integer	23734	Translation lookaside buffer for data (dTLB) read misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	dTLB-stores	Integer	23734	Translation lookaside buffer for data (dTLB) writes by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	dTLB-store-misses	Integer	23734	Translation lookaside buffer for data (dTLB) write misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	dTLB-prefetches	Integer	23734	Translation lookaside buffer for data (dTLB) prefetch accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	dTLB-prefetch-misses	Integer	23734	Translation lookaside buffer for data (dTLB) prefetch misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	iTLB-loads	Integer	23734	Translation lookaside buffer for instructions (iTLB) read accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	iTLB-load-misses	Integer	23734	Translation lookaside buffer for instructions (iTLB) read misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	branch-loads	Integer	23734	Branch prediction unit read accesses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	branch-load-misses	Integer	23734	Branch prediction unit read misses by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	cpu-cycles	Integer	23734	Total CPU cycles by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	instructions	Integer	23734	Retired instructions by a CPU core	jevents from pmu-tools	Note: these can be affected by various issues, most notably hardware interrupt counts.	Dependent on jevents library to read the metric value
Metric	cache-references	Integer	23734	Cache accesses per CPU core. Usually this indicates Last Level Cache accesses but this may vary depending on CPU type.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	cache-misses	Integer	23734	Cache read misses by a CPU core. Usually this indicates Last Level Cache misses.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	branches	Integer	23734	Retired branch instructions by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	branch-misses	Integer	23734	Mispredicted branch instructions by a CPU core	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	bus-cycles	Integer	23734	Bus cycles per CPU core, which can be different from total cycles.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	cpu-clock	Integer	23734	Reports the CPU clock, a high-resolution per-CPU timer, by a CPU core. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	task-clock	Integer	23734	Reports a clock count specific to the task that is running, by a CPU core. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	context-switches	Integer	23734	Number of context switches per CPU core. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	cpu-migrations	Integer	23734	Number of times the process has migrated to a new CPU, by a CPU core. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	page-faults	Integer	23734	Number of page faults by a CPU core. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	minor-faults	Integer	23734	Number of minor page faults by a CPU core. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	major-faults	Integer	23734	Number of major page faults by a CPU core. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	alignment-faults	Integer	23734	Number of alignment faults by a CPU core. These happen when unaligned memory accesses happen. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Metric	emulation-faults	Integer	23734	Number of emulation faults by a CPU core. The kernel sometimes traps on unimplemented instructions and emulates them for user space. Software event provided by the kernel.	jevents from pmu-tools		Dependent on jevents library to read the metric value
Input	Cores	Integer Array as String	"[0-12]" or "1,2,3"	The list of CPU core(s) to be provided as input by the user for which the corresponding metrics are required	None	None	Configuration input in the plugin .conf file
Input	Configuration Interval	Integer	1 or 10	The interval in seconds at which the metrics need to be collectd	None	None	Configuration input in the plugin .conf file
Input	Report Hardware Cache Events	Boolean	true/false	Report hardware CPU cache events, list in comments	None	None	L1-dcache-loads, L1-dcache-load-misses, L1-dcache-stores, L1-dcache-store-misses, L1-dcache-prefetches, L1-dcache-prefetch-misses, L1-icache-loads, L1-icache-load-misses, L1-icache-prefetches, L1-icache-prefetch-misses, LLC-loads, LLC-load-misses, LLC-stores, LLC-store-misses, LLC-prefetches, LLC-prefetch-misses, dTLB-loads, dTLB-load-misses, dTLB-stores, dTLB-store-misses, dTLB-prefetches, dTLB-prefetch-misses, iTLB-loads, iTLB-load-misses, branch-loads, branch-load-misses
Input	Report Kernel PMU Events	Boolean	true/false	Report generalized hardware CPU events. Not all of these are available on all platforms. List in comments.	None	None	cpu-cycles, instructions, cache-references, cache-misses, branches, branch-misses, bus-cycles
Input	Report Software Events	Boolean	true/false	Software events provided by the kernel. List in comments.	None	None	cpu-clock, task-clock, context-switches, cpu-migrations, page-faults, minor-faults, major-faults, alignment-faults, emulation-faults
Input	Event List	String	"pmu-events/GenuineIntel-6-55-core.json"	Path to file with custom hardware events. The should containt description and definition for events available for given CPU type.	None	File should be valid for supported CPU type.	Valid file for current CPU type can be obtained with use of event_download tool: https://raw.githubusercontent.com/andikleen/pmu-tools/master/event_download.py
Input	Hardware Events	String Array	L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS	Custom hardware events for given CPU type. Names of events must be available in "Event List" json file.	event_download.py tool	No	If there are more events than counters, the kernel uses time multiplexing. With multiplexing, at the end of the run, the counter is scaled basing on total time enabled vs time running.

Example graph¶

Instructions (counter) corresponding to perf metric PERF_COUNT_HW_INSTRUCTIONS.

History¶

Cores option is available since release 5.8.1.
Support for uncore multi pmu was added in 5.11

Dependencies¶

jevents

Configuration examples¶

This page contains some example configurations for the Intel PMU plugin. This page is meant as a cookbook, so if you have a configuration for an aspect not handled here or a daemon not present, please feel free to add anything that's useful for you.

Collect only HWCacheEvents¶

 <Plugin intel_pmu>
  HWCacheEvents true
  KernelPMUEvents false
  SWEvents false
 </Plugin>

Collect only KernelPMUevents¶

 <Plugin intel_pmu>
  HWCacheEvents false
  KernelPMUEvents true
  SWEvents false
 </Plugin>

Collect only SWEvents¶

 <Plugin intel_pmu>
  HWCacheEvents false
  KernelPMUEvents false
  SWEvents true
 </Plugin>

Enable hardware specific events¶

A single value or comma separated list of values should be used for HWSpecificEvents parameter.

 <Plugin intel_pmu>
  HWCacheEvents false
  KernelPMUEvents false
  SWEvents false
  HWSpecificEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS"
 </Plugin>

Configuration¶

Configuration options · from collectd.conf(5)

See this section in the full configuration reference

The intel_pmu plugin collects performance counters data on Intel CPUs using Linux perf interface. All events are reported on a per core basis.

Synopsis:

<Plugin intel_pmu>
  ReportHardwareCacheEvents true
  ReportKernelPMUEvents true
  ReportSoftwareEvents true
  EventList "/var/cache/pmu/GenuineIntel-6-2D-core.json"
  HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
  Cores "0-3" "4,6" "[12-15]"
  DispatchMultiPmu false
</Plugin>

Options:

ReportHardwareCacheEvents false|true

Enable or disable measuring of hardware CPU cache events: - L1-dcache-loads - L1-dcache-load-misses - L1-dcache-stores - L1-dcache-store-misses - L1-dcache-prefetches - L1-dcache-prefetch-misses - L1-icache-loads - L1-icache-load-misses - L1-icache-prefetches - L1-icache-prefetch-misses - LLC-loads - LLC-load-misses - LLC-stores - LLC-store-misses - LLC-prefetches - LLC-prefetch-misses - dTLB-loads - dTLB-load-misses - dTLB-stores - dTLB-store-misses - dTLB-prefetches - dTLB-prefetch-misses - iTLB-loads - iTLB-load-misses - branch-loads - branch-load-misses

ReportKernelPMUEvents false|true

Enable or disable measuring of the following events: - cpu-cycles - instructions - cache-references - cache-misses - branches - branch-misses - bus-cycles

ReportSoftwareEvents false|true

Enable or disable measuring of software events provided by kernel: - cpu-clock - task-clock - context-switches - cpu-migrations - page-faults - minor-faults - major-faults - alignment-faults - emulation-faults

EventList filename

JSON performance counter event list file name. To be able to monitor all Intel CPU specific events JSON event list file should be downloaded. Use the pmu-tools event_download.py script to download event list for current CPU.

HardwareEvents events

This field is a list of event names or groups of comma separated event names. This option requires EventList option to be configured.

Cores cores groups

All events are reported on a per core basis. Monitoring of the events can be configured for a group of cores (aggregated statistics). This field defines groups of cores on which to monitor supported events. The field is represented as list of strings with core group values. Each string represents a list of cores in a group. If a group is enclosed in square brackets each core is added individually to a separate group (that is statistics are not aggregated). Allowed formats are: 0,1,2,3 0-10,20-18 1,3,5-8,10,0x10-12 [4-15,32-63]

If an empty string is provided as value for this field default cores configuration is applied - that is separate group is created for each core.

DispatchMultiPmu false|true

Enable or disable dispatching of cloned multi PMU for uncore events. If disabled only total sum is dispatched as single event. If enabled separate metric is dispatched for every counter.